Field-programmable gate arrays are a particular type of programmable device that provides functional flexibility to the user. As opposed to an application-specific integrated circuit (ASIC) or other similar device in which the functionality is “hard-wired” in the device, an FPGA allows a user to program the device to support a relatively wide range of functionality. One of the main advantages of FPGAs over ASICs is that a single FPGA hardware design can provide user-programmable functionality to support many different applications, while an ASIC is limited to the particular functions that are hard-wired into the device at the time of fabrication.
In order to communicate with other components, an FPGA must be able to transmit outgoing signals to and/or receive incoming signals from those other components. There are many different signaling standards in use today that define protocols for signal communications between components. For example, different signaling standards may rely on symmetric or non-symmetric differential or complementary signaling having different sets of voltage levels corresponding to data true, data complement, and the intermediate common-mode voltage.
A particular signal-processing system might conform to a particular signaling standard for its inter-component communications. In that case, all of the components in the system would ideally be compatible with that particular signaling standard so that all inter-component communications within the system would conform to that signaling standard.
In the past, an FPGA would be designed to operate in systems that conform to a particular set of signaling standards. Such an FPGA would be able to transmit and/or receive signals conforming to those particular signaling standards. In order for that same FPGA to be configured to operate in a system that conforms to some other signaling standard (outside of the supported set), additional hardware, external to the FPGA (e.g., a board-level discrete device), would have to be provided in order to convert (1) incoming signals (i.e., signals transmitted to the FPGA from other system components) from the system's signaling standard to the different signaling standard supported by the FPGA and (2) outgoing signals (i.e., signals transmitted from the FPGA and intended for other system components) from the FPGA's signaling standard to the system's different signaling standard. Alternatively, a different FPGA would have to be designed to support the system's different signaling standard.
As silicon devices become smaller and faster, device I/O speeds and signal integrity requirements increase. One thing that helps signal integrity and speed is to use terminated interface standards, such as Stub Series Termination Logic or High-Speed Transceiver Logic. The use of impedance and termination helps (1) match board traces thereby reducing reflections and (2) dampen ringing. The closer the termination is to the receiver and driver circuits, the greater the effect. When routing a bus from one chip to another, it helps to match the routing between the bus signals, to minimize the delay skew between the different board routes. Having the termination on the chip rather than on the board reduces the amount of board routing, thereby keeping the skew to a minimum.
One of the most common termination schemes used today is to terminate the board trace at the driver or receiver or both using a resistor to halve the power supply of the driving circuit. The terminating resistor value is set to be equal to the board trace impedance, which is typically 50 ohms. Devices that implement these terminations on the silicon chip, typically use thevenin equivalent circuits, which use more power than non-thevenin termination schemes.
As device sizes shrink, the cost of silicon area increases and the signaling requirements of I/O circuits also increase. In particular, I/O circuits are often required to run faster and support multiple interface standards that require the circuits to use device technologies that do not shrink as fast as the cores devices on the silicon chip.
Low-voltage differential signal schemes are often used to meet increased signaling speed requirements. The reduced signal swing of differential standards allows them to run faster. The differential attribute of the signaling allows them to work in noise environments due to their common-mode noise immunity. Differential signaling schemes work on the premise of one signal's relative potential to the other. Common-mode phenomena such as ground bounce and power droop affect both differential signals together. As the common mode of the differential signals is disturbed, the relative potential of one signal to the other is not. This allows differential signaling to work where single-ended or terminated standards might not.
One way to increase signal integrity of high-speed differential signaling is to use common-mode termination for the differential termination of the receiver. Conventionally, a differential resistor with a common-mode termination uses an external capacitor connected to ground, which allows AC-effects of the common-mode noise to be shunted to ground. Conventional common-mode termination requires extra pads on the silicon to be bonded for the external capacitors.
Due to increased I/O speed requirements and signal integrity requirements, interface standards continue to change. Although differential signaling offers higher speeds and better common-mode noise rejection, they come at a cost of double the interface signals and pads. There is still a realm of performance that requires good speed and signal integrity without the cost of doubling the interface size. Terminated single-ended standards are used for just such interfaces.
One of the newer interface standards requires a dynamic termination scheme involving a bidirectional interface, where the termination is off when the output driver is on and the termination is on when the output driver is off, to enable receipt of an incoming signal. In these types of bidirectional interfaces, a conventional approach is to have each side terminate when it is not driving. This is not available on board because the board does not have access to a signal that states when one or the other device is driving on the board.
As mentioned above, one approach being used today is on-chip thevenin termination with the cost of increased power. By increasing the number of power and ground pins on a chip to meet the power requirements for thevenin termination, the signal-pin-to-power-pin ratio is reduced and therefore the number of signals available on the device for I/O interfaces is reduced. Another approach being used today is off-chip, on-board terminations. These devices are external discrete devices on the board, although this comes at the cost of increased board complexity, routing, and skew, and therefore increased design time and financial cost.
External discrete-device differential termination resistors are also available today but are farther from the receiver and therefore reduce the effectiveness of signal integrity at the receiver. Differential termination schemes are available today with and without common-mode termination both on- and off-chip. The devices available today are costly in resources due to the fact that the differential termination is either a separate circuit on the silicon device with no sharing of resources or a thevenin equivalent scheme with a fixed common-mode termination voltage. The negative effect of a fixed common-mode termination is that the driver's common mode may be different, which could impact the driver's duty cycle and performance. If the driver had a more advance design with an op-amp to control the common mode of the output signal, then the op-amp could go unstable.